`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:04:35 07/06/2014 
// Design Name: 
// Module Name:    mod_7 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mod_7_12bit (
	input [11:0] in,
	output [2:0] out
    );

wire [11:0] temp;
wire [5:0] a = in[11:6];
wire [5:0] b = in[5:0];

wire [2:0] a_mod_7;
wire [2:0] b_mod_7;

mod_7_6bit mod7_1 (
	.in (a),
	.out (a_mod_7)
);

mod_7_6bit mod7_2 (
	.in (b),
	.out (b_mod_7)
);

assign temp = a_mod_7 * ((1 << 6) % 7) + b_mod_7;

mod_7_6bit mod7_3 (
	.in (temp),
	.out (out)
);

endmodule
